Circuit for generating a series of cipher pulses

ABSTRACT

15. A message transmission installation comprising at least two stations each capable of acting as a transmitter and receiver, each station comprising apparatus capable of acting as a transmitter and receiver of information, a mixer, and a circuit for generating reproducible series of code pulses having a long period, said circuit comprising a binary counting chain having at least 20 members, connections connecting each of said members to a respective mixer, a plurality of shift register elements constituting a shift register chain, connections connecting each mixer to a respective shift register element, to a previous shift register element in the chain and to a switching distributor the state of which is determined by a switching criterion, the arrangement being such that the mixers mix the information content of one counting member of the counting chain with the information of one shift register element and this mixed information is delivered to the next shift register element if the state of the switching distributor is in accordance with the switching state of the corresponding member of the counting chain, and that the information of one shift register element is delivered to the next shift register element unchanged if the state of the switching distributor differs from the switching state of the corresponding member of the counting chain.

i ited tates 'Patet Ehrat July 18, 1972 [54] CIRCUIT FOR GENERATING ASERIES OF CIPIER PULSES Kurt Ehrat, Scheuchzerstrasse 28, Zurich,Switzerland Filed: Jan. 8, 1963 Appl.No.: 250,119

[ 72] Inventor:

Primary Examiner-Richard A. Farley Attorney-Pierce, Schefiler & ParkerCODE PULSE EXEMPLARY CLAIM 15. A message transmission installationcomprising at least two stations each capable of acting as a transmitterand receiver, each station comprising apparatus capable of acting as atransmitter and receiver of information, a mixer, and a circuit forgenerating reproducible series of code pulses having a long period, saidcircuit comprising a binary counting chain having at least 20 members,connections connecting each of said members to a respective mixer, aplurality of shift register elements constituting a shift registerchain, connections connecting each mixer to a respective shift registerelement, to a previous shift register element in the chain and to aswitching distributor the state of which is determined by a switchingcriterion, the arrangement being such that the mixers mix theinformation content of one counting 'member of the counting chain withthe information of one shift register element and this mixed informationis delivered to the next shift register element if the state of theswitching distributor is in accordance with the switching state of thecorresponding member of the counting chain, and that the information ofone shift register element is delivered to the next shift registerelement unchanged if the state of the switching distributor differs fromthe switching state of the corresponding member of the counting chain.

15 Claims, 7 Drawing Figures CODE PULSE GENERATOR ER Q GENERATOR EP so zws so zws LOCK M RS- -MRS SIP TI TI I TRANSMlT TER/ gg 'gg C IP KI PR\ECEIVER II MIXING I3 MIXING I4 CIRCUIT Patented July 18, 1972 5Sheets-Sheet 1.

CODE PULSE GENERATOR RECEIVER P P I [I 6- S K WU w 7 mm Ml C 3 W c M flmm 1 mm T C P \I C I T J n mm mm mm C MIXING AND CALCULATING CIRCUITTRANSMITTER FIG] Jiwmvfm T J M u h fi p m b T P z E m m 5 4 G. 5 T S llz 4 4 M L F Z4 m w M m L Z J m s W 2 2 I m m w 52 4 z 1 1 m L 2 E. m s 1M l.l.l .HL 8 N u m Kurt Ehraf Patented July 18, 1972 3,678,198

5 Sheets-Sheet 5 FIGA SIP

lfurfi Ehraf [L /Lou JVL WXD 1 0% Patented July 18, 1972 5 Sheets-SheetI l l fullllll|lllrlll1llllllll|lllllIlllllL LL 1 r m 0E H t r U KPatented July 18, 1972 3,678,198

5 Sheets-Sheet 5 Sum 4 6/ CIRCUIT FOR GENERATING A SERIES OF CIPHERPULSES This invention relates to mixing and calculating circuits forgenerating reproducible series of cipher pulses having a long period,which forms constituents of cipher pulse generators. Cipher pulsegenerators are used in ciphering messages, particularly messages whichare transmitted in the form of pulses.

In the ciphering of such messages, the individual pulses (orcombinations of pulses) are first mixed at a transmitter with as randomas possible a series of corresponding pulses (or combinations ofpulses), called the cipher pulses (or cipher pulse combinations) and aretransmitted in the form of the new pulses obtained by the mixing. At thereceiving end, the original message is reproduced with the aid of asecond identical series of cipher pulses. The said cipher pulse seriesmust be generated in identical format the transmitter and receiver. Thispurpose is served by the likewise identical cipher pulse generatorswhich are present at the transmitter and receiver.

The cipher pulse series (code pulse program), and hence also the actualcipher pulse generator, must satisfy specific requirements in orderreliably to exclude the possibility of the message being decipheredalong the transmission path by unauthorized persons. First of all, theperiod of cycle length of the cipher pulse series i.e., the period oftime within which the cipher pulse series does not repeat itself must besufficiently great to make it impossible for the entire cipher pulseseries to be reproduced sufiiciently quickly to be of use, even when themost rapid electronic means are used. Furthermore, the distribution ofthe pulses within the cipher pulse series should be random (statistical)to the utmost possible extent. The cipher pulse series must also becreated according to such complicated rules that it is impossible from aknowledge of the series to deduce the state of the individual circuitelements of the cipher pulse generators. Furthermore, the cipher pulseseries must be reproducible i.e., a quite definite and unequivocal pulseseries must be produced for a specific initial state of a cipher pulsegenerator.

According to the present invention there is provided a circuit forgenerating reproducible series of code pulses having a long period, saidcircuit comprising a binary counting chain having at least 20 members,connections connecting each of said members to a respective mixer, aplurality of shift register elements constituting a shift registerchain, connections connecting each mixer to a respective shift registerelement, to a previous shift register element in the chain and to aswitching distributor the state of which is determined by a criterion,the arrangement being such that the mixers mix the information contentof one counting member of the counting chain with the information of oneshift register element at a time and this mixed information is deliveredto the next shift register element if the state of the switchingdistributor is in accordance with the switching state of thecorresponding member of the counting chain.

The mixers used may advantageously be so-called modulus 2 mixers.However it is also possible to use, instead of such modulus 2 mixers,AND-gates and OR-gates known from the logical art, equal numbers ofAND-gates and OR-gates being advantageously used in each case. In bothcases that is to say, both where modulus 2 mixers are used and also whenequal numerical quantities of AND-gates and OR-gates are used, theaverage frequency of occurrence of the states and 1 remainsapproximately unchanged. Therefore, if a negative counter-likecountingchain such as that described in my copending U.S. Pat.application, Ser. No. 227,344 filed Oct. 1, 1962 be used, wherein thefrequency of occurrence of the states 0" and 1" is approximately ofequal magnitude, then the said frequency distribution is, on average,unmodified by the mixers.

In order to enable the invention to be more readily understood,reference will now be made to the accompanying drawings, whichillustrate diagrammatically and byway of example some embodimentsthereof, and in which:

FIG. I is a block circuit diagram of a message transmission installationwith automatic ciphering and deciphering;

FIG. 2 is a simplified circuit diagram of a mixing and calculatingcircuit;

FIG. 3 is a simplified circuit diagram of another mixing and calculatingcircuit;

FIG. 4 shows a greatly simplified circuit diagram similar to FIG. 3 inorder to explain the switching cycle;

FIG. 5 is a simplified circuit diagram of yet another mixing andcalculating circuit; and

FIGS. 6 and 7 show two circuit details, FIG. 6 showing a coincidencedetector and FIG. 7 showing a modulus 2 mixing circuit.

Referring now to FIG. 1, there is shown a message transmissioninstallation in which clear message pulses KIP (clear pulse program)emanating from a transmitter 11 pass to a modulus 2 adder 12, where theyare mixed with a cipher pulse series SIP of a cipher pulse generator8G,, and the mixture the enciphered pulse program CIP is transmitted toa receiver, where it is mixed in a modulus 2 adder 13 with a cipherpulse series SIP of a cipher pulse generator 86 whereupon the clearpulse program KIP is recovered and fed to a message receiver l4. Sincethe cipher pulse series SIP constitutes a continuously changing seriesof cipher pulses, synchronization of the cipher pulses at thetransmitting end SG and the receiving end 86 is necessary. Thissynchronization may be controlled for example by timing pulses TI whichare generated in a clock 15 and are added to the ciphered pulse programCIP by means of a mixing circuit 16. On the receiving side, the timingpulses TI are then taken out again from the ciphered message by means ofa mixing circuit 17 and supplied to the cipher pulse generator 86 forsynchronization. Each of the cipher pulse generators consistssubstantially of a counter circuit ZWS and of a mixing and calculatingcircuit MRS. It is advantageous to use a counting chain such as thatdescribed in my aforesaid Patent Application No. 227,334 because thelatter .fulfils the condition that O and l pulses occur with almostequals frequency even over short periods.

A simple type of mixing and calculating circuit, and its cooperationwith the counter circuit, will now be described with reference to FIG.2. Referring now to FIG. 2, a counter circuit ZWS consists of n countingelements 2,, Z Z 2,,. Each counting element has a respective connectionE,, E E E,,, acting as outputs from the counter circuit ZWS and asinputs to the mixing and calculating circuit MRS. Each of the inputs E,Q, E, is capable of assuming the states 0 or 1. Advantageously, binarycounter circuits ZWS are used, which are connected together in themanner described in my aforesaid copending patent application, Ser. No.227,344 and have the principle of operation therein set forth. In thecase of such a counting chain, the switching state of practically allthe members of the counting chain changes from counting step to countingstep. Furthermore, the counting chain reverts to its initial state onlyafter passing through all the possible combinations of positions.

The counting process is controlled by the timing pulses Tl so that, forexample, each timing pulse initiates a counting step. The inputs E E EE, (outputs from the counter circuit) are taken in the mixing andcalculating circuit MRS to input gate circuits TE,, TE TE TE,,, thesecond inputs of which are fed from a switching distributor SV. Theoutputs of the gate circuits are taken to modulators M8,, M5 M8,, MSwhich are, for example, modulus 2 adders, which may be constructed inthe manner shown in FIG. 7. The modulators are connected into a shiftregister having shift register stages SR SR SR SR,,, substantially sothat each modulator is located between two shift register stages. Bymeans of the timing pulses TI, which act as shift pulses, theinformation in the shift register stages is shifted in the direction ofthe arrow 21 (to the right in FIG. 2), namely from one shift registerstage into the next one on its right hand side in each case and for eachtiming pulse. During shifting, the shifted information is mixed in themodulator MS with the information present at the output of the gate TE,and the mixed information passes to the shift register stage on theright. At the right hand end, that is to say, at its output, the shiftregister chain is connected a divider circuit U, which consists, forexample, of a normal flipflop divider stage, the information from theoutput 22 of which is mixed in a modulus 2 mixer or adder MU with theinformation from the output of the shift register chain and fed back viaa line 23 to the input of the shift register chain. Simultaneously, thepulse program is passed out from the line 23 as the cipher pulse programSIP.

The principle of operation of the circuit shown in FIG. 2 is as follows.Due to the adoption of the binary system, the switching states of theindividual members of the counting chain and of the individual shiftregister stages may be either or 1. These switching states can be variedin the rhythm of the timing pulses TI, which advance the counting in thecounting chain from counting step to counting step, and which areresponsible for shifting the switching states in the shift registerchain that is to say, for displacing the switching state of a shiftregister stage to the next shift register stage located to the rightthereof for one timing pulse. By means of the mixers of the modulatorsM8,, M MS MS,,, it is possible for the switching states of the counterstages to be mixed via the gates TE with those of the shift registerstages. Mixing occurs in every case when the first inputs of the inputgates TE,, TE. TE are open that is to say, whenever the said firstinputs are brought into the switching state 1. Control of the said firstinputs is exercised by the switching distributor SV the state of whichis determined by a switching criterion such as are indicated by thearrows 24. For example, the circuit may function in such a manner thatfrom time to time all the input gates TE are simultaneously opened, sothat at that instant the switching states of all the counter elementsare simultaneously mixed with those of the shift register stages, orthat only certain input gates are open, so that only certain switchingstates of counter elements are mixed with switching states of the shiftregister stages.

The divider stage U likewise has two possible switching states 0 or 1and changes its switching state whenever the switching state 1 occurs atthe input 25. Continuous totalling without carrying takes place in thesaid divider stage. The output 22 of the divider stage U is mixed in themodulus 2 adder MU with the particular switching state of the output onthe right hand side of the shift register chain, whereby a pulse seriestotally difierent from the said output is produced in the line 23, isdelivered as a cipher pulse series SIP and is fed via the modulator MS,to the first shift register stage SR,. A divider stage U together withthe modulus 2 adder MU, produces a great additional complication of thecipher pulse series, and also makes it impossible for the switchingstates of the individual shift register stages to be deduced from thecipher pulse series. It is easy to see that the cipher pulse series SIPthus obtained has been produced according to extremely complex rules,and also that, by the use ofa negative-counterlike chain such as thatdescribed in the Specification of the aforesaid patent application, Ser.No. 227,344 and in conjunction with modulus 2 mixers, an equally greatprobability of the occurrence of the switching states 0 or 1, and anextremely good approximately random pulse distribution (0 or I) isachieved. Finally it will be seen that, by the action of the countercircuit, the cipher pulse series will possess an extremely long cycleperiod if there is a sufficient number of counter elements.

The circuit shown in FIG. 3 is of similar construction to that shown inFIG. 2. But in this case, additionally to the circuit of FIG. 2, acoincidence detector circuit KDS is provided. This circuit consists ofcoincidence detectors KD,, KD KD KD, and of gate circuits TD,, TD,,,TD,, TD,,. The circuit of an individual coincidence detector isindicated by way of example in FIG. 6, and the principle of operationofsuch a coincidence detector is as follows:

If both inputs ED, and ED, (input arrows) have the same switching statethat is to say, the switching state of both inputs is l or the switchingstate of both inputs is 0 then the switching state I occurs at theoutput AD of the coincidence detector. But if the two inputs ED, and EDhave different switching states then the switching state 0 occurs at theoutput AD. Coincidence of the switching states of the two inputs istherefore marked by a l at the output AD.

In FIG. 3, the switching state of a shift register stage is compared ineach case with that of a counting element, and the coincidenceindication is fed to the gate circuit TD, to TD,,. A sole exception isconstituted by the coincidence detector KD,,, which in this caseascertains coincidences between the switching state of the shiftregister stage SR, and the shift register stage SR,,. The gate circuitTD, transmits when the switching state 1 occurs at its input i.e., whenthe coincidence detector KD, delivers a l at its output, which is thecase when the shift register stage SR, and counting element 2, exhibitthe same switching state (coincidence). The gate circuit TD, is open ortransmits when KD, and KDg are simultaneously in coincidence that is tosay. that it is necessary simultaneously for Z, and SR, on the one handand Z and SR on the other hand to be in coincidence. Analogously, threecoincidences must be fulfilled simultaneously in the case of gatecircuit TD,,, four coincidences simultaneously in the case of gatecircuit TD,,, and n (5 as shown) coincidences simultaneously in the caseof gate circuit TD,,, in order to bring their outputs to switchingstate 1. The outputs 31 to 35 of the gate circuits TD, TD,, act as firstinputs of the input gate circuits TE,, TE, TE,,. In the form ofconstruction illustrated in FIG. 3, the coincidence detector circuitproduces the result that the counter state of Z, is mixed into the shiftregister chain via TE,, MS, whenever Z, and SR, are in coincidence, andfurthermore that the switching state of the counting element 2 is mixedinto the shift registers chain (via T5 MS when Z, and SR, and also Z andSR are simultaneously coincident. Furthermore it produces the resultthat the switching state of the counting element Z is mixed into theshift register chain via TE MS when Z, and SR,, Z and SR,, and Z and SR,are simultaneously coincident, and so on. Groups of coincidencedetectors of different group size l, 2, 3 detectors) are thereforeformed, so that a switching operation i.e., the mixing of a switchingstate of a counting element into the shift register chain is initiatedvia the gate circuits TD, TD,, whenever all the coincidence detectors ofthe group concerned exhibit coincidence simultaneously. Since the groupsof coincidence detectors have different sizes (1, 2, 3, 4 n coincidencedetectors), the frequency of the switching processes thus initiated isalso different. For example, in the case of a totally randomdistribution of the switching states in the elements of the countingchain and in the shift register stages, the average frequency ofcoincidence between 2, and SR, would be one-half (50 percent). Likewiseof course the average frequency of coincidence between Z and SR, orbetween 2 and SR,; but the average frequency of simultaneous coincidencebetween Z, and SR, on the one hand and Z and SR on the other hand is 1:2and the average frequency of simultaneous coincidence between 2,, SR,, Zand SR and Z and SR, is 1:2", and so on. The simultaneous coincidence ofa group of three coincidence detectors is 4 times less frequent thanthat having only one coincidence detector. The switching processes whichare initiated by the outputs of the gates TD,, TD TD,, (lines 31, 32,33, 34, 35) thus exhibit greatly different average frequencies. Thecoincidence detector circuit is a feedback circuit, which verysubstantially increases the complexity of the cipher pulse series. It issimultaneously possible for all the switching states of the countingelements to be mixed into the shift register chain via an input line S0to the switching distributor.

The circuit shown in FIG. 4 has a similar structure and principle ofoperation to that shown in FIG. 3. It is proposed to show, withreference to FIG. 4, an example of the switching cycle over a pluralityof timing pulses, and the generation of a cipher pulse series SIP. Forthe sake of simplicity, the number of counting elements and of shiftregister stages has here been restricted to 4. (This would be too fewaccording to the invention.) The switching cycle can easily beascertained by the laws of logic circuits, and is recorded in thefollowing Table l.

TABLE 1 Schedule of the chronological cycle of switching states of theexample according to FIG. 4.

TI 1 2 3 4 5 6 7 8 9 10 ll l2 l3 l4 I6 l7 I8 40 I y 40 40 40 I I I I Z,O I 0 l O l O l O l O l 0 l O l 0 l Z 0 l l O O l l O 0 l l O O l l 0 OI Z O l l 0 I 0 0 l 0 l I 0 I 0 0 l O I Z, O I l 0 l O l O l 0 O l O l 0l 0 1 SR, 0 O 0 O 0 l l O l l 0 l l l O O O l SR O 0 0 0 O 0 l l O l l 0I l l O 0 0 SR, 0 O 0 0 0 l O l l 0 O O 0 l l I O 0 SR, 0 0 O l O l l Ol l O 0 I 0 O l l 0 KD, l O I O l I 0 0 O l l l 0 l l O l l KD, l O 0 ll O l O l l l l O l I l l 0 KB, 1 O O l O 0 l l 0 O O l 0 0 0 l l O KD,l O 0 O O 0 0 l l 0 l 0 O 0 l l O 0 TD, 1 O l 0 l l O 0 O l l l O l l 0l 1 TD, 1 O O 0 l O 0 O 0 l l l O l l 0 l 0 TD,, 1 O O O O O 0 O 0 O 0 l0 0 0 0 l 0 TD,, 1 O O 0 0 0 0 O O 0 O O O 0 0 0 l 0 TE, 0 0 O 0 O O 0 O0 O O O O O 0 O O 0 TE, 0 O 0 0 0 0 0 0 O O O O 0 0 0 0 0 0 TE, 0 0 O Ol O O O O l l O O O O 0 0 0 TE, 0 O l O l O O 0 0 O O l O l O O O l U 00 0 l l O l l O l l l O 0 0 l 0 0 SIP 0 0 O 0 l l 0 l l O l l l 0 InTable l, the switching state at the outputs of the individual switchingelements is shown as O or I. The timing pulses Tl, which bring about themodification of the switching states, are indicated schematically in thetop line and are numbered from one to 18 (chronological sequence). Thecounting elements Z, to 2,, shift register stages SR, SR,, and thedivider stage U are storing switching elements, whereas the coincidencedetectors KD, to KD the gates TE, to TE and the gates TD, to TD, arenon-storing. At the commencement of the switching cycle recorded by wayof example in the schedule, the output of the counting elements Z, to Z,are at O of the shift register stage SR, to SR, are at 0, of the dividerstage U is at 0,

whereby the switching states of the outputs of the remaining circuitelements are fixed by the laws of logic, namely the outputs of thecoincidence detectors KD, to KD, are at l, the outputs of TD, to TD, areat 1, and the outputs of TE, to TE are at 0 The formation of a cipherpulse SIP will now be ascertained by way of example with reference toFIG. 4 and to Table l. The initial switching state of the circuit willbe assumed to correspond to that after the eight beat pulse (columnbetween 8th and 9th beat pulses in Table I). Therefore, under theseconditions, for example, the output of Z, is at O 2 is at O 2,, is at 0L is at l. the output of SR, is at l SR is at 0 SR is at 1 SR, is at 1.this gives the output of KD, as 0, (since no coincidence between Z, andSR, the output of KD, as 1 (since 2, and SR, are in coincidence) and soon. The outputs of TD, to TD, and of TE, to TE, are all found to be 0,and if the output of U 0, then an SIP state of l is obtained (mixture ofU with SR, in MU).

The subsequent timing pulse (9th Tl) changes Z, from O to l Z from 0 to1 2,, from 0 to I Z, from 1 to 0.

(Column between 9th and 10th timing pulse in Table I).

The switching state of SR, is shifted unchanged (since TE 0) to SR,,,likewise the switching state of SR to SR, (because TE, 0).

The switching state of SR, l) is mixed with U in MU 0) and TE, 0) and isshifted as 1 into SR,. The divider U changes its switching state at the9th TI, since the output of SR, was previously I and the gate TU istherefore open. By this means, the output of U becomes 1, and since SR,,output is again I, the output of MU becomes 0 i.e.,

A number of delay circuits, not shown, are also requisite to the properfunctioning of the circuit.

The circuit shown in FIG. 5 is again of another structure to that inFIG. 3, but it exhibits certain modifications and additions. Thus, thegate circuit with the gates TD,, TD,, TD,, TD,, in the coincidencedetector circuit in FIG. 3 is replaced by a gate circuit with gates TK,,TK TI( TK, TK,, in FIG. 5. However, the principle of operation of thisgate circuit is the same as of that in FIG. 3.

Thus, for example, the gate TK, delivers an output pulse 1, when thecoincidence detector KD, alone has coincidence. The gate TK, delivers anoutput pulse when two coincidence detectors (KD, and KD,,,) havecoincidence simultaneously, the gate TK delivers an output pulse whenthree coincidence detectors (KD,,, KD and KD,,,) have coincidence, andso on. The outputs of the gates in the coincidence circuit pass viaOR-gates T0,, T0,, T0,, T0,,, to the input gates (as first input) TE,,TE TE, TE where they in turn control the switching processes that is tosay, the mixing of the switching states of the counting elements intothe shift registers. The majority of the coincidence detectors shownascertain coincidence each between one counting element and one shiftregister stage. By contrast, the coincidence detector KD, ascertainscoincidence between two counting elements, namely Z, and 2,, whereas thecoincidence detectors KD, and KD, each ascertain coincidence between twoshift register stages. In contradistinction to the form of constructionshown in FIG. 3, three self-contained shift register chains are providedin the construction shown in FIG. 5 instead of only one. The top shiftregister chain possesses the shift register stages SR,, SR,, SR SR,,,and is closed via a circuit containing a divider U, and a modulator MU,back to the modulator M5,. The central shift register chain having shiftregister stages SR SR,,, SR,,, SR,, is closed via the circuit containinga divider stage U and a modulator MU The third shift register chainhaving the shift register stages SR SR SR,,, and SR is closed via thecircuit containing a divider stage U and a modulator MU The cipher pulseseries SIP is again derived at the output of the modulators (MU MU MU Inthis case therefore, it is possible to obtain simultaneously threeparallel outputs of cipher pulse series. The circuit example in FIG. 5moreover contains an interchanger circuit VS having interchanger gatesTV,, TV TV TV TV and TV and divider U The divider U.,, which is forexample a flip-flop circuit, has two outputs, of which one is at and theother at l at any time. Each input pulse to the divider U interchangesthe switching states at the two outputs. For example, if the right handoutput of the divider U is at 1, then the interchanger gates TV,, TV TVare conductive and the shift register stage SR passes on itsinformation, upon shifting, to SR SR to SR and SR to SR On the otherhand, ifthe left hand output of the divider U is at I, then theinterchanger gates TV TV TV are conductive and the switching state SRpasses to SR that of SR to SR and that of SR to SR... The change in theswitching state in the divider U has thus brought about an interchangeof the flow of information in the three shift register chains. Controlof the divider U is exercised by a pulse at the output of the gate TK inthe coincidence detector circuit that is to say, whenever KD KD KD KDand KD have coincidence simultaneously. A further additional circuitarrangement as compared with the construction shown in F IG. 3 is theconnection of a binary counter 82 at the output of the three shiftregister chains. The binary counter BZ consists here of the three binarycounting stages ZB 2B ZB and therefore possesses a counting period of 28. The counting steps occur in rhythm with the timing pulses T]. Theprinciple of operation of this binary counter is as follows:

When the maximum binary number 111 is reached, the output gate TBbecomes conductive (at the moment when a timing pulse TI occurs), andthe switching processes are initiated via the line SO and the OR-gatesT0,, T0 T0 etc., which may be for example that the switching states ofthe counting elements are mixed into the shift register chain via theinput gates TE,, TE etc., and furthermore that the interchanger circuitVS is interchanged via the divider U But simultaneously the output pulseof the output gate T8,, passing through the line 64 and the input gatesTB TB and TB;,, causes the switching states of the outputs of the shiftregister chains (output of SR1 SR and SR to be imprinted into theindividual counting elements ZB,, 2B and ZB via lines 61, 62 and 63.This imprinted binary number is now an initial position, from whence thebinary counter 82 is stepped on by the action of the timing pulses Tluntil the binary counter again reaches the maximum binary number 111 andthe process already described is repeated. This circuit arrangement alsomakes a very substantial contribution towards increasing the complexityof the switching cycle i.e., to the complexity of the cipher pulseseries.

The invention is of course not restricted to the number of circuitelements indicated in the example. For example, it would also bepossible to provide a plurality of interchanger circuits instead of onlyone, and in the same way five or any desired number of shift registerchains might be provided instead ofonly three.

What is claimed is:

l. A circuit for generating reproducible series of cipher pulses havinga long period, said circuit comprising a binary counting chain having atleast members, connections connecting each of said members to arespective mixer, a plurality of shift register elements constituting ashift register chain, connections connecting each mixer to a respectiveshift register element, to a previous shift register element in thechain, and to a switching distributor the state of which is determinedby a switching criterion, the arrangement being such that the mixers mixthe information content of one counting member of the counting chainwith the information of one shift register element and this mixedinformation is delivered to the next shift register element if the stateof the switching distributor is in accordance with the switching stateof the corresponding member of the counting chain, and that theinformation of one shift register element is delivered to the next shiftregister element unchanged if the state of the switching distributordiffers from the switching state of the corresponding member of thecounting chain.

2. The circuit of claim 1, wherein said mixers are modulus 2 mixers.

3. The circuit of claim 1, wherein each mixer is composed ofsubstantially equal numbers of AND-gates and OR-gates.

4. A circuit for generating reproducible series of cipher pulses havinga long period, comprising at least 20 counting members constituting abinary counting chain, at least 20 mixers each connected to a respectivecounting member, a plurality of shift register elements constitutingtogether with the mixers a shift register chain, the mixers and theshift register elements being connected alternately in series, at leastone binary divider stage coupled to at least one point of the shiftregister, and at least one further mixer the input of which is connectedto the output of a respective binary divider stage and the output ofwhich is connected to at least one further shift register element, thearrangement being such that, the mixers mix the information content ofone binary divider stage with the information of one shift registerelement at a time and deliver the mixed information to the next shiftregister element.

5. The circuit of claim 4, wherein said mixers are modulus 2 mixers.

6. The circuit of claim 4, wherein the code pulse program is obtainedfrom said further mixer and is derived from the information content ofthe divider stage and the shift register stage.

7. The circuit of claim 4, wherein the shift register chain is dividedinto a plurality of self contained shift register chains.

8. The circuit of claim 7 and further comprising at least oneinterchanger circuit for interchanging the flow of information of oneshift register chain to another shift register chain, interchangementtaking place at least between any element of one shift register chainwith any element of another shift register chain.

9. A circuit for generating reproducible series of cipher pulses havinga long period, comprising at least 20 counting members constituting abinary counting chain, at least 20 mixers each connected to a respectivecounting member, a plurality of shift register elements constitutingtogether with the mixers a shift register chain, the mixers and theshift register elements being connected alternately in series, at leastone binary divider stage coupled to at least one point of the shiftregister, at least one further mixer the input of which is connected tothe output of a respective binary divider stage and the output of whichis connected to at least one further shift register element, a pluralityof gate circuits, and a plurality of coincidence detectors, the gatecircuits and coincidence detectors being interconnected between thecounting members and the mixers in such manner that, in the case ofcoincidence between the switching states of two freely selected membersof the counting chain and elements of the shift register, a switchingpulse is delivered at the output of the coincidence detector, differentsized groups of coincidence detectors being associated through the gatecircuits in such manner that switching processes are initiated throughthe outputs of the gate circuits whenever there is simultaneous deliveryof switching pulses by all the coincidence detectors belonging to therelevant group.

10. The circuit of claim 9, wherein the shift register chain is dividedinto a plurality of self-contained shift register chains.

11. The circuit of claim 10, and further comprising at least oneinterchanger circuit for interchanging the flow of information of oneshift register chain to another register shift register chain,interchangement taking place at least between any element of one shiftregister chain with any element of another shift register chain.

12. A circuit for generating reproducible series of cipher pulses havinga long period, comprising at least 20 counting members constituting abinary counting chain, at least 20 mixers each connected to a respectivecounting member, a plurality of shift register elements constitutingtogether with the mixers a shift register chain, the mixers and theshift register elements being connected alternately in series, at leastone binary divider stage coupled to at least one point of the shiftregister, at least one further mixer the input of which is connected tothe output of a respective binary divider stage and the output of whichis connected to at least one further shift register element, a pluralityof gate circuits, a plurality of coincidence detectors, the gatecircuits and coincidence detectors being interconnected between thecounting members and the mixers in such manner that, in the case ofcoincidence between the switching states of two freely selected membersof the counting chain and elements of the shift register, a switchingpulse is delivered at the output of the coincidence detector, differentsized groups of coincidence detectors being associated through the gatecircuits in such manner that switching processes are initiated throughthe outputs of the gate circuits whenever there is simultaneous deliveryof switching pulses by all the coincidence detectors belonging to therelevant group, at least one binary counter, means for imprinting theinformation content of at least one plurality of shift register stagesinto the binary counter at intervals whereby the binary counter runs inthe rhythm of the counting steps up to its maximum number, meansoperable by the binary counter when it reaches its maximum number toinitiate a switching process to imprint the information content presentat that moment at the shift register stage as a new binary number intothe binary counter.

13. The circuit of claim 12, wherein the shift register chain is dividedinto a plurality of self-contained shift register chains.

14. The circuit of claim 13, and further comprising at least oneinterchanger circuit for interchanging the flow of information of oneshift register chain to another shift register chain, interchangementtaking place at least between any element of one shift register chainwith any element of another shift register chain.

15. A message transmission installation comprising at least two stationseach capable of acting as a transmitter and receiver, each stationcomprising apparatus capable of acting as a transmitter and receiver ofinformation, a mixer, and a circuit for generating reproducible seriesof code pulses having a long period, said circuit comprising a binarycounting chain having at least 20 members, connections connecting eachof said members to a respective mixer, a plurality of shift registerelements constituting a shift register chain, connections connectingeach mixer to a respective shift register element, to a previous shifiregister element in the chain and to a switching distributor the stateof which is determined by a switching criterion, the arrangement beingsuch that the mixers mix the information content of one counting memberof the counting chain with the information of one shift register elementand this mixed information is delivered to the next shift registerelement if the state of the switching distributor is in accordance withthe switching state of the corresponding member of the counting chain,and that the information of one shift register element is delivered tothe next shift register element unchanged if the state of the switchingdistributor differs from the switching state of the corresponding memberof the counting chain.

1. A circuit for generating reproducible series of cipher pulses havinga long period, said circuit comprising a binary counting chain having atleast 20 members, connections connecting each of said members to arespective mixer, a plurality of shift register elements constituting ashift register chain, connections connecting each mixer to a respectiveshift register element, to a previous shift register element in thechain, and to a switching distributor the state of which is determinedby a switching criterion, the arrangement being such that the mixers mixthe information content of one counting member of the counting chainwith the information of one shift register element and this mixedinformation is delivered to the next shift register element if the stateof the switching distributor is in accordance with the switching stateof the corresponding member of the counting chain, anD that theinformation of one shift register element is delivered to the next shiftregister element unchanged if the state of the switching distributordiffers from the switching state of the corresponding member of thecounting chain.
 1. A circuit for generating reproducible series ofcipher pulses having a long period, said circuit comprising a binarycounting chain having at least 20 members, connections connecting eachof said members to a respective mixer, a plurality of shift registerelements constituting a shift register chain, connections connectingeach mixer to a respective shift register element, to a previous shiftregister element in the chain, and to a switching distributor the stateof which is determined by a switching criterion, the arrangement beingsuch that the mixers mix the information content of one counting memberof the counting chain with the information of one shift register elementand this mixed information is delivered to the next shift registerelement if the state of the switching distributor is in accordance withthe switching state of the corresponding member of the counting chain,anD that the information of one shift register element is delivered tothe next shift register element unchanged if the state of the switchingdistributor differs from the switching state of the corresponding memberof the counting chain.
 2. The circuit of claim 1, wherein said mixersare modulus 2 mixers.
 3. The circuit of claim 1, wherein each mixer iscomposed of substantially equal numbers of AND-gates and OR-gates.
 4. Acircuit for generating reproducible series of cipher pulses having along period, comprising at least 20 counting members constituting abinary counting chain, at least 20 mixers each connected to a respectivecounting member, a plurality of shift register elements constitutingtogether with the mixers a shift register chain, the mixers and theshift register elements being connected alternately in series, at leastone binary divider stage coupled to at least one point of the shiftregister, and at least one further mixer the input of which is connectedto the output of a respective binary divider stage and the output ofwhich is connected to at least one further shift register element, thearrangement being such that, the mixers mix the information content ofone binary divider stage with the information of one shift registerelement at a time and deliver the mixed information to the next shiftregister element.
 5. The circuit of claim 4, wherein said mixers aremodulus 2 mixers.
 6. The circuit of claim 4, wherein the code pulseprogram is obtained from said further mixer and is derived from theinformation content of the divider stage and the shift register stage.7. The circuit of claim 4, wherein the shift register chain is dividedinto a plurality of self contained shift register chains.
 8. The circuitof claim 7 and further comprising at least one interchanger circuit forinterchanging the flow of information of one shift register chain toanother shift register chain, interchangement taking place at leastbetween any element of one shift register chain with any element ofanother shift register chain.
 9. A circuit for generating reproducibleseries of cipher pulses having a long period, comprising at least 20counting members constituting a binary counting chain, at least 20mixers each connected to a respective counting member, a plurality ofshift register elements constituting together with the mixers a shiftregister chain, the mixers and the shift register elements beingconnected alternately in series, at least one binary divider stagecoupled to at least one point of the shift register, at least onefurther mixer the input of which is connected to the output of arespective binary divider stage and the output of which is connected toat least one further shift register element, a plurality of gatecircuits, and a plurality of coincidence detectors, the gate circuitsand coincidence detectors being interconnected between the countingmembers and the mixers in such manner that, in the case of coincidencebetween the switching states of two freely selected members of thecounting chain and elements of the shift register, a switching pulse isdelivered at the output of the coincidence detector, different sizedgroups of coincidence detectors being associated through the gatecircuits in such manner that switching processes are initiated throughthe outputs of the gate circuits whenever there is simultaneous deliveryof switching pulses by all the coincidence detectors belonging to therelevant group.
 10. The circuit of claim 9, wherein the shift registerchain is divided into a plurality of self-contained shift registerchains.
 11. The circuit of claim 10, and further comprising at least oneinterchanger circuit for interchanging the flow of information of oneshift register chain to another register shift register chain,interchangement taking place at least between any element of one shiftregister chain with any element of another shift register chain.
 12. Acircuit for generating reProducible series of cipher pulses having along period, comprising at least 20 counting members constituting abinary counting chain, at least 20 mixers each connected to a respectivecounting member, a plurality of shift register elements constitutingtogether with the mixers a shift register chain, the mixers and theshift register elements being connected alternately in series, at leastone binary divider stage coupled to at least one point of the shiftregister, at least one further mixer the input of which is connected tothe output of a respective binary divider stage and the output of whichis connected to at least one further shift register element, a pluralityof gate circuits, a plurality of coincidence detectors, the gatecircuits and coincidence detectors being interconnected between thecounting members and the mixers in such manner that, in the case ofcoincidence between the switching states of two freely selected membersof the counting chain and elements of the shift register, a switchingpulse is delivered at the output of the coincidence detector, differentsized groups of coincidence detectors being associated through the gatecircuits in such manner that switching processes are initiated throughthe outputs of the gate circuits whenever there is simultaneous deliveryof switching pulses by all the coincidence detectors belonging to therelevant group, at least one binary counter, means for imprinting theinformation content of at least one plurality of shift register stagesinto the binary counter at intervals whereby the binary counter runs inthe rhythm of the counting steps up to its maximum number, meansoperable by the binary counter when it reaches its maximum number toinitiate a switching process to imprint the information content presentat that moment at the shift register stage as a new binary number intothe binary counter.
 13. The circuit of claim 12, wherein the shiftregister chain is divided into a plurality of self-contained shiftregister chains.
 14. The circuit of claim 13, and further comprising atleast one interchanger circuit for interchanging the flow of informationof one shift register chain to another shift register chain,interchangement taking place at least between any element of one shiftregister chain with any element of another shift register chain.